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S29WS-P
MirrorBit(R) Flash Family
S29WS512P, S29WS256P, S29WS128P 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
S29WS-P Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29WS-P_00
Revision A
Amendment 11
Issue Date September 28, 2007
Data
Sheet
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local sales office.
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S29WS-P
S29WS-P_00_A11 September 28, 2007
S29WS-P
MirrorBit(R) Flash Family
S29WS512P, S29WS256P, S29WS128P 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
Data Sheet
Features
Single 1.8 V read/program/erase (1.70-1.95 V) 90 nm MirrorBitTM Technology Simultaneous Read/Write operation with zero latency Random page read access mode of 8 words with 20 ns intra page access time 32 Word / 64 Byte Write Buffer Sixteen-bank architecture consisting of 32/16/8 Mwords for 512/256/128P, respectively Four 16 Kword sectors at both top and bottom of memory array 510/254/126 64Kword sectors (WS512/256/128P) Programmable linear (8/16/32) with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and 128 words for customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of top and bottom sectors Dual boot sector configuration (top and bottom) Handshaking by monitoring RDY Offered Packages
- WS512P/WS256P/WS128P: 84-ball FBGA (11.6 mm x 8 mm)
Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings ACC input pin to reduce factory programming time Support for Common Flash Interface (CFI)
General Description
The Spansion S29WS512/256/128P are Mirrorbit(R) Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for today's demanding wireless applications requiring higher density, better performance and lowered power consumption.
Performance Characteristics
Read Access Times Speed Option (MHz) Max. Synch Access Time (tIACC) Max. Synch. Burst Access, ns (tBACC) Max OE# Access Time, ns (tOE) Max. Asynch. Access Time, ns (tACC) 104 103.8 7.6 7.6 80 Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VACC) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 40 s 9.4 s 6 s 350 ms 600 ms Current Consumption (typical values) Continuous Burst Read @ 104 MHz Simultaneous Operation 104 MHz Program Standby Mode 36 mA 40 mA 20 mA 20 A
Publication Number S29WS-P_00
Revision A
Amendment 11
Issue Date September 28, 2007
Data
Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2. 3. 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 MCP Look-ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 13
5. 6. 7.
Additional Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Synchronous (Burst) Read Mode & Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 Simultaneous Read/Program or Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Power-up/Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 19 20 20 28 32 34 51 51 52 52 52 54 55 55 56 58 58 59 60 62 62 62 62 62 63 63 64 64 66 66 66 67 68 68 68 69
8.
9.
10.
11.
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S29WS-P_00_A11 September 28, 2007
Data
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11.8 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.10 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12. 13. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
September 28, 2007 S29WS-P_00_A11
S29WS-P
5
Data
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Figures
Figure 4.1 Figure 4.2 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 8.1 Figure 8.2 Figure 8.3 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 11.12 Figure 11.13 Figure 11.14 Figure 11.15 Figure 11.16 Figure 11.17 Figure 11.18 Figure 11.19 Figure 11.20 Figure 11.21 Figure 11.22 Figure 11.23 Figure 11.24 Figure 11.25 84-Ball Fine-Pitch Ball Grid Array, 512, 256 & 128 Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBH084--84-ball Fine-Pitch Ball Grid Array, 11.6 x 8 mm MCP Compatible Package. . . . . Synchronous/Asynchronous State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around . . . . . . . . . . . . . . . . 8-word Linear Single Data Read Synchronous Burst without Wrap Around . . . . . . . . . . . . . Asynchronous Read Mode (AVD# Toggling - Case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Mode (AVD# Toggling - Case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Mode (AVD# Toggling - Case 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Mode (AVD# tied to CE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 28 29 35 39 42 48 54 57 60 66 66 68 68 69 69 71 71 72 73 73 74 74 75 77 78 79 79 80 80 81 81 82 82 83
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S29WS-P_00_A11 September 28, 2007
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Tables
Table 2.1 Table 6.1 Table 6.2 Table 6.3 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 Table 7.12 Table 7.13 Table 7.14 Table 7.15 Table 7.16 Table 7.17 Table 7.18 Table 7.19 Table 7.20 Table 7.21 Table 7.22 Table 7.23 Table 7.24 Table 7.25 Table 7.26 Table 7.27 Table 7.28 Table 7.29 Table 7.30 Table 7.31 Table 7.32 Table 7.33 Table 7.34 Table 7.35 Table 7.36 Table 7.37 Table 7.38 Table 7.39 Table 7.40 Table 7.41 Table 7.42 Table 7.43 Table 7.44 Table 7.45 Table 7.46 Table 7.47 Table 7.48 Table 8.1 Table 8.2 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 S29WS512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 S29WS256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 S29WS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Page Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Address Latency for 11 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Address Latency for 10 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 09 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 11 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 10 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 11 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 10 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Reset (LLD Function = lld_ResetCmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
September 28, 2007 S29WS-P_00_A11
S29WS-P
7
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Sheet
Table 8.3 Table 8.4 Table 8.5 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 Table 11.7 Table 12.1 Table 12.2 Table 12.3 Table 12.4 Table 12.5 Table 12.6
S29WS512P Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 S29WS256P Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 S29WS128P Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Non-Continuous Burst Mode with Wrap Around Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . .70 Continuous Burst Mode with No Wrap Around Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .70 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8
S29WS-P
S29WS-P_00_A11 September 28, 2007
Data
Sheet
1.
Ordering Information
The ordering part number is formed by a valid combination of the following:
S29WS
512
P
xx
BA
W
00
0 Packing Type 0 = Tray (standard; see note 1) 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number (Chip Enable Options) 00 = Default Temperature Range W = Wireless (-25C to +85C) Package Type And Material BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package Speed Option (Burst Frequency) 0L = 54 MHz 0P = 66 MHz 0S = 80 MHz AB = 104 MHz Process Technology P = 90 nm MirrorBit(R)Technology Flash Density 512= 512 Mb 256= 256 Mb 128= 128 Mb Device Family S29WS =1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
S29WS512P Valid Combinations (Notes 1, 2) Base Ordering Part Number S29WS512P S29WS256P Advance S29WS128P Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S29 and packing type designator from ordering part number. 0L, 0P, 0S, AB BAW (Lead (Pb)-free Compliant), BFW (Lead (Pb)-free) 0, 2, 3 (Note 1) 00 11.6 mm x 8 mm 84-ball MCP-Compatible Product Status Speed Option Package Type, Material, & Temperature Range Packing Type Model Numbers Package Type (Note 2) 11.6 mm x 8 mm 84-ball MCP-Compatible
September 28, 2007 S29WS-P_00_A11
S29WS-P
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Data
Sheet
2.
Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions
Symbol AMAX-A0 DQ15-DQ0 CE# OE# WE# VCC VCCQ VSS NC RDY CLK Type Input I/O Input Input Input Supply Supply Supply No Connect Output Input Description Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and 22 for WS128P) Data input/output. Chip Enable. Asynchronous relative to CLK. Output Enable. Asynchronous relative to CLK. Write Enable. Device Power Supply Device Input/Output Power Supply (Must be ramped simultaneously with VCC) Ground. Not connected internally. Ready. Indicates when valid burst data is ready to be read. Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid. Indicates to device that the valid address is present on the address inputs. AVD# Input When low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be latched at the next active clock edge. When high, device ignores address inputs. RESET# WP# ACC RFU Input Input Input Reserved Hardware Reset. Low = device resets and returns to reading array data. Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use (see MCP look-ahead pinout for use with MCP).
10
S29WS-P
S29WS-P_00_A11 September 28, 2007
Data
Sheet
3. Block Diagrams
VCC
Y-Decoder
Bank Address
Latches and Control Logic
VSS VCCQ
DQ15-DQ0
Bank 0
AMAX-A0 X-Decoder OE#
Bank Address
Latches and Control Logic
Y-Decoder
DQ15-DQ0
Bank 1
WP# ACC RESET# WE# CEx# AVD# RDY DQ15-DQ0
AMAX-A0
X-Decoder DQ15-DQ0 Status
STATE CONTROL & COMMAND REGISTER
AMAX-A0
Control
X-Decoder
Latches and Control Logic
Y-Decoder
Bank Address
Bank (n-1)
DQ15-DQ0
AMAX-A0
X-Decoder
Bank Address
Latches and Control Logic
Y-Decoder
Bank (n)
DQ15-DQ0
Notes: 1. AMAX-A0 = A24-A0 for the WS512P, A23-A0 for the WS256P, and A22-A0 for the WS128P. 2. n = 15 for WS512P / WS256P / WS128P.
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29WS-P.
4.1
Related Documents
The following documents contain information relating to the S29WS-P devices. Click on the title or go to www.spansion.com to download the PDF file, or request a copy from your sales office. Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
September 28, 2007 S29WS-P_00_A11
S29WS-P
11
Data
Sheet
Figure 4.1 84-Ball Fine-Pitch Ball Grid Array, 512, 256 & 128 Mb
(Top View, Balls Facing Down, MCP Compatible)
A1 NC B2 AVD# C2 WP# D2 A3 E2 A2 F2 A1 G2 A0 H2 F-CE# J2 RFU K2 RFU L2 RFU M1 NC B3 VSS C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 RFU D4 RFU E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 VSS B5 RFU C5 ACC D5 RESET# E5 RDY F5 RFU G5 RFU H5 DQ3 J5 VCC K5 DQ11 L5 VCC B6 VCC C6 WE# D6 RFU E6 A20 F6 A23 G6 RFU H6 DQ4 J6 RFU K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 A24 H8 DQ15 J8 DQ7 K8 DQ14 L8 VCCQ B9 RFU C9 RFU D9 A15 E9
A10 NC
Legend
Reserved for Future Use
Do Not Use
Ground A21 F9 A22 G9 A16 H2 RFU J9 VSS K9 RFU L9 RFU M10 NC Power
Notes: 1. Balls F6 and G8 are RFU on the WS128P. 2. Ball G8 is RFU on the WS256P. 3. VCC pins must ramp simultaneously.
12
S29WS-P
S29WS-P_00_A11 September 28, 2007
Data
Sheet
Figure 4.2 VBH084--84-ball Fine-Pitch Ball Grid Array, 11.6 x 8 mm MCP Compatible Package
0.05 C (2X)
D
A
D1 e
10 9
e
8 7 6
7
SE E1
E
5 4 3 2 1 M L K J H G F E D C B A
A1 CORNER
A1 CORNER
INDEX MARK
B
10
0.05 C (2X)
6
SD
0.08 M C 0.15 M C A B
7
NXb
TOP VIEW
BOTTOM VIEW
A
A1
SEATING PLANE
A2
0.10 C
C
0.08 C
SIDE VIEW
NOTES: PACKAGE JEDEC VBH 084 N/A 11.60 mm x 8.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.33 MIN --0.18 0.62 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 --0.80 BSC. 0.40 BSC. (A2-A9, B10-L10, M2-M9, B1-L1) 0.43 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note: BSC is an ANSI standard for Basic Space Centering.
4.3
MCP Look-ahead Connection Diagram
Spansion Inc. provides this standard look-ahead connection diagram that supports NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and pSRAM densities up to 4 Gigabits NOR Flash and pSRAM and data storage densities up to 4 Gigabits The physical package outline may vary between connection diagrams and densities. The connection diagram for any MCP, however, is a subset of the pinout.
September 28, 2007 S29WS-P_00_A11
S29WS-P
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Data
Sheet
In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls are reserved; do not connect them to any other signal. For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless Solutions with Spansion Products application note (publication number: Design_Scalable_Wireless_AN), available on the web or through a Spansion sales office.
14
S29WS-P
S29WS-P_00_A11 September 28, 2007
Data
Sheet
5.
Additional Resources
Visit www.spansion.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices Understanding Burst Mode Flash Memory Devices Simultaneous Read/Write vs. Erase Suspend/Resume MirrorBit(R) Flash Memory Write Buffer Programming and Page Buffer Read Design-In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers True Flash File System
CAD Modeling Support
VHDL and Verilog IBIS ORCAD(R) Schematic Symbols
Technical Support
Contact your local sales office or contact Spansion Inc. directly for additional technical support: http://www.spansion.com/flash_memory_products/support/ses/index.html
Spansion Inc. Locations
915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited Cube-Kawasaki 9F/10F, 1-14 Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa, 210-0024, Japan Phone: 044-223-1700 (active from Nov.28th) http://www.spansion.com
September 28, 2007 S29WS-P_00_A11
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15
Data
Sheet
6.
Product Overview
The S29WS-P family consists of 512, 256, and 128 Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for today's wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable.
6.1
Memory Map
The S29WS512/256/128P Mbit devices consist of 16 banks organized as shown in Tables 6.1-6.3. Table 6.1 S29WS512P Sector & Memory Address Map
Bank Size Sector Count Sector Size (KB) 32 32 4 32 4 MB 32 128 ... 31 0 SA002 SA003 SA004 ... 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh ... Sector Starting Address - Sector Ending Address (see note) Bank Sector/ Sector Range SA000 SA001 Address Range 000000h-003FFFh 004000h-007FFFh Sector Starting Address - Sector Ending Address Notes
128 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SA034 SA035-SA066 SA067-SA098 SA099-SA130 SA131-SA162 SA163-SA194 SA195-SA226 SA227-SA258 SA259-SA290 SA291-SA322 SA323-SA354 SA355-SA386 SA387-SA418 SA419-SA450 SA451-SA482 SA483
1F0000h-1FFFFFh 200000h-3FFFFFh
............
E00000h-FFFFFFh 1000000-11FFFFF ...............
First Sector, Starting Address - Last Sector, Ending Address (see note)
1C00000h-1DFFFFFh 1E00000h-1E0FFFFh Sector Starting Address - Sector Ending Address (see note)
31
128
SA513 4 MB 4 32 SA516 SA517 15 SA514 SA515
...
1FE0000h-1FEFFFFh 1FF0000h-1FF3FFFh 1FF4000h-1FF7FFFh 1FF8000h-1FFBFFFh 1FFC000h-1FFFFFFh
Sector Starting Address - Sector Ending Address
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005-SA033) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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Table 6.2 S29WS256P Sector & Memory Address Map
Bank Size Sector Count Sector Size (KB) Bank Sector/ Sector Range SA000 SA001 4 2 MB 32 0 SA002 SA003 15 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SA004 to SA018 SA019 to SA034 SA035 to SA050 SA051 to SA066 SA067 to SA082 SA083 to SA098 SA099 to SA114 SA115 to SA130 SA131 to SA146 SA147 to SA162 SA163 to SA178 SA179 to SA194 SA195 to SA210 SA211 to SA226 SA227 to SA242 SA243 to SA257 SA258 2 MB 4 32 SA260 SA261 FF8000h-FFBFFFh FFC000h-FFFFFFh 15 SA259 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 3F0000h-3FFFFFh 400000h-40FFFFh to 4F0000h-4FFFFFh 500000h-50FFFFh to 5F0000h-5FFFFFh 600000h-60FFFFh to 6F0000h-6FFFFFh 700000h-70FFFFh to 7F0000h-7FFFFFh 800000h-80FFFFh to 8F0000h-8FFFFFh 900000h-90FFFFh to 9F0000h-9FFFFFh A00000h-A0FFFFh to AF0000h-AFFFFFh B00000h-B0FFFFh to BF0000h-BFFFFFh C00000h-C0FFFFh to CF0000h-CFFFFFh D00000h-D0FFFFh to DF0000h-DFFFFFh E00000h-E0FFFFh to EF0000h-EFFFFFh F00000h-F0FFFFh to FE0000h-FEFFFFh FF0000h-FF3FFFh FF4000h-FF7FFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (see note) Address Range 000000h-003FFFh 004000h-007FFFh Contains four smaller sectors at bottom of addressable memory. Notes
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005-SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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Table 6.3 S29WS128P Sector & Memory Address Map
Bank Size Sector Count Sector Size (KB) 32 32 4 1 MB 32 32 7 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 32 1 MB 4 32 32 SA132 SA133 7F8000h-7FBFFFh 7FC000h-7FFFFFh 32 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 SA002 SA003 SA004 to SA010 SA011 to SA018 SA019 to SA026 SA027 to SA034 SA035 to SA042 SA043 to SA050 SA051 to SA058 SA059 to SA066 SA067 to SA074 SA075 to SA082 SA083 to SA090 SA091 to SA098 SA099 to SA106 SA107 to SA114 SA115 to SA122 SA123 to SA129 SA130 SA131 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh to 070000h-07FFFFh 080000h-08FFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 170000h-17FFFFh 180000h-18FFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 270000h-27FFFFh 280000h-28FFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 370000h-37FFFFh 380000h-38FFFFh to 3F0000h-3FFFFFh 400000h-40FFFFh to 470000h-47FFFFh 480000h-48FFFFh to 4F0000h-4FFFFFh 500000h-50FFFFh to 570000h-57FFFFh 580000h-58FFFFh to 5F0000h-5FFFFFh 600000h-60FFFFh to 670000h-67FFFFh 680000h-68FFFFh to 6F0000h-6FFFFFh 700000h-70FFFFh to 770000h-77FFFFh 780000h-78FFFFh to 7E0000h-7EFFFFh 7F0000h-7F3FFFh 7F4000h-7F7FFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (see note) Bank Sector/ Sector Range SA000 SA001 Address Range 000000h-003FFFh 004000h-007FFFh Contains four smaller sectors at bottom of addressable memory. Notes
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005-SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
7. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Table 12.1 on page 85 and Table 12.2 on page 87). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
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7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state of each control pin for any particular operation. Table 7.1 Device Operations
Operation Asynchronous Read - Addresses Latched Asynchronous Read AVD# Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations Latch Starting Burst Address by CLK Advance Burst read to next address Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L X L X X X H H H H H X X L H X X Addr In X X X Addr In Output Invalid Output Valid HIGH Z HIGH Z Output Invalid = toggle. X H HIGH Z HIGH Z X H H H L H CE# L L L L H X OE# L L H H X X L X X X X X X WE# H H CLK X X X L L AVD# Amax-A0 Addr In Addr In Addr In Addr In X X DQ15-0 Output Valid Output Valid Input Valid I/O HIGH Z HIGH Z RDY H H H H HIGH Z HIGH Z RESET# H H H H H
Legend: L = Logic 0, H = Logic 1, X = can be either VIL or VIH., Note: Address is latched on the rising edge of clock.
= rising edge,
= high to low,
7.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address, preventing changes to the address lines from effecting the address being accessed.. Data is output on DQ15-DQ0 pins after the access time (tACC) has elapsed from the falling edge of AVD#, or the last time the address lines changed while AVD# was low.
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7.3
Page Mode Read
The device is capable of fast page mode read. This mode provides fast (tPACC) random read access speed for locations within a page. Address bits Amax-A3 select an 8 word page, and address bits A2-A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. It does not matter if AVD# stays low or toggles. However, the address input must be always valid and stable if AVD# is low during the page read. The random or initial page access is tACC or tCE (depending on how the device was accessed) and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted (=VIH), the reassertion of CE# for subsequent access has access time of tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax-A3 constant and changing A2-A0 to select the specific word within that page. Table 7.2 Page Select
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
7.4
Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operations and can be automatically enabled for burst mode. To enter into synchronous mode, the configuration register will need to be set. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. Once the system has written the Set Configuration Register command sequence, the device is enabled for synchronous reads only. The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that data is output only at the rising edge of the clock. RDY indicates the initial latency.
7.4.1
Latency Tables for Variable Wait State
The following tables show the latency for variable wait state in a continuous Burst operation Table 7.3 Address Latency for 11 Wait States
Word 0 1 2 3
Initial Wait D0 D1 D2 D3 11 ws D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 1 ws D2 D3 D4 D5 D6 D7 1 ws 1 ws D3 D4 D5 D6 D7 1 ws 1 ws 1 ws D4 D5 D6 D7 1 ws 1 ws 1 ws 1 ws D5 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D8 D8 D8 D8 D9 D9 D9 D9 D9 D9 D9 D9 D10 D10 D10 D10 D10 D10 D10 D10 ... ... ... ... ... ... ... ... D124 D124 D124 D124 D124 D124 D124 D124 D125 D125 D125 D125 D125 D125 D125 D125 D126 D126 D126 D126 D126 D126 D126 D126 D127 D127 D127 D127 D127 D127 D127 D127 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 D0 D0 D0 D0
4 5 6 7
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Table 7.4 Address Latency for 10 Wait States
Word 0 1 2 3 10 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 ... ... ... ... D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 ... ... ... ... D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0
Table 7.5 Address Latency for 09 Wait States
Word 0 1 2 3 9 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 ... ... ... ... D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 ... ... ... ... D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
Table 7.6 Address Latency for 8 Wait States
Word 0 1 2 3 8 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9
Table 7.7 Address Latency for 7 Wait States
Word 0 1 2 3 7 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10
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Table 7.8 Address Latency for 6 Wait States
Word 0 1 2 3 6 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11
Table 7.9 Address Latency for 5 Wait States
Word 0 1 2 3 5 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11
Table 7.10 Address Latency for 4 Wait States
Word 0 1 2 3 4 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 D13 D13 D13 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11
Table 7.11 Address Latency for 3 Wait States
Word 0 1 2 3 3 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 D9 D10 D11 D11 D10 D11 D12 D12 D11 D12 D13 D13 D12 D13 D14 D14 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11
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7.4.2
Latency for Boundary Crossing during First Read
The following tables show the latency at End of Word Line for boundary corssing during First Read in continuous burst operation Table 7.12 Address Latency for 11 Wait States
Word 0 1 2 3 11 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0
Table 7.13 Address Latency for 10 Wait States
Word 0 1 2 3 10 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0
Table 7.14 Address Latency for 9 Wait States
Word 0 1 2 3 9 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws D0 D0 D0 D0
Table 7.15 Address Latency for 8 Wait States
Word 0 1 2 3 8 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 D0 D0 D0 D0 D1 D1 D1
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Table 7.16 Address Latency for 7 Wait States
Word 0 1 2 3 7 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 D0 D0 D127 D0 D1 D1 D0 D1 D2 D2
Table 7.17 Address Latency for 6 Wait States
Word 0 1 2 3 6 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3
Table 7.18 Address Latency for 5 Wait States
Word 0 1 2 3 5 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 D4 D4 D4 D4 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3
Table 7.19 Address Latency for 4 Wait States
Word 0 1 2 3 4 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 D12 D12 D12 D4 D5 D5 D5 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3
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Table 7.20 Address Latency for 3 Wait States
Word 0 1 2 3 3 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 D0 D0 D127 D0 D1 D1 D0 D1 D2 D2 D1 D2 D3 D3 D2 D3 D4 D4 D3 D4 D5 D5 D4 D5 D6 D6 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3
7.4.3
Latency at End of Word Line for Boundary Crossing After Second Read in Continuous Burst Operation
The following tables show the latency for boundary crossing after Second Read in a continuous Burst operation. Table 7.21 Address Latency for 11 Wait States
Word 0 1 2 3
Initial Wait D112 D113 D114 D115 11 ws D116 D117 D118 D119 D113 D114 D115 D116 D117 D118 D119 1 ws D114 D115 D116 D117 D118 D119 1 ws 1 ws D115 D116 D117 D118 D119 1 ws 1 ws 1 ws D116 D117 D118 D119 1 ws 1 ws 1 ws 1 ws D117 D118 D119 1 ws 1 ws 1 ws 1 ws 1 ws D118 D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D120 D120 D120 D120 D121 D121 D121 D121 D121 D121 D121 D121 D122 D122 D122 D122 D122 D122 D122 D122 D123 D123 D123 D123 D123 D123 D123 D123 D124 D124 D124 D124 D124 D124 D124 D124 D125 D125 D125 D125 D125 D125 D125 D125 D126 D126 D126 D126 D126 D126 D126 D126 D127 D127 D127 D127 D127 D127 D127 D127 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 D0 D0 D0 D0
4 5 6 7
Table 7.22 Address Latency for 10 Wait States
Word 0 1 2 3 10 ws 4 5 6 7 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D112 D113 D114 D115 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0
Table 7.23 Address Latency for 9 Wait States
Word 0 1 2 3 9 ws 4 5 6 7 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D113 D114 D115 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
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Table 7.24 Address Latency for 8 Wait States
Word 0 1 2 3 8 ws 4 5 6 7 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D113 D114 D113 D113 D114 D115 D114 D114 D115 D116 D115 D115 D116 D117 D116 D116 D117 D118 D117 D117 D118 D119 D118 D118 D119 1 ws D119 D119 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
Table 7.25 Address Latency for 7 Wait States
Word 0 1 2 3 7 ws 4 5 6 7 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
Table 7.26 Address Latency for 6 Wait States
Word 0 1 2 3 6 ws 4 5 6 7 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
Table 7.27 Address Latency for 5 Wait States
Word 0 1 2 3 5 ws 4 5 6 7 D112 D113 D114 D115 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
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Table 7.28 Address Latency for 4 Wait States
Word 0 1 2 3 4 ws 4 5 6 7 D112 D112 D113 D114 D113 D113 D114 D115 D114 D114 D115 D116 D115 D115 D116 D117 D116 D116 D117 D118 D117 D117 D118 D119 D118 D118 D119 1 ws D119 D119 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
Table 7.29 Address Latency for 3 Wait States
Word 0 1 2 3 4 ws 4 5 6 7 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0
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7.5
Synchronous (Burst) Read Mode & Configuration Register
See Configuration Registers on page 31, and Table 12.1, Memory Array Commands on page 85, for further details. Figure 7.1 Synchronous/Asynchronous State Diagram
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (CR15 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (CR15 = 1)
Synchronous Read Mode Only
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Figure 7.2 Synchronous Read Flow Chart
Note: Setup Configuration Register parameters
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Set Configuration Register Command and Settings: Address 555h, Data D0h Address X00h, Data CR
Command Cycle CR = Configuration Register Bits CR15-CR0
Load Initial Address Address = RA
RA = Read Address
Wait tIACC + Programmable Wait State Setting
CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles
Read Initial Data RD = DQ[15:0]
RD = Read Data
Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing
Refer to the Latency tables.
Read Next Data RD = DQ[15:0]
Delay X Clocks Crossing Boundary? No
Yes
End of Data?
Yes
Completed
7.5.1
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wraps around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET#= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary with in the same bank, but not into a program or erase suspended sector (as mentioned above), additional latency cycles are required as reflected by the configuration register table (Table 7.31). If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse.
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7.5.2
8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 7.30). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 383Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group.
Note
In this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. Table 7.30 Burst Address Groups
Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,... Group Address Ranges
7.5.3
8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 3Ch43h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state.
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7.5.4
Configuration Registers
This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The Configuration Register can also be read using a command sequence (see Table 12.1 on page 85). The following list describes the register settings. Table 7.31 Configuration Register
CR Bit CR0.15 CR0.14 CR1.0 CR0.13 CR0.12 Function Set Device Read Mode Reserved (Not used) Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (Default) 0 = Reserved (Default) 1 = Reserved 0000 = initial data is valid on the 2nd rising CLK edge after addresses are latched 0001 = initial data is valid on the 3rd rising CLK edge after addresses are latched 0010 = initial data is valid on the 4th rising CLK edge after addresses are latched 0011 = initial data is valid on the 5th rising CLK edge after addresses are latched 0100 = initial data is valid on the 6th rising CLK edge after addresses are latched 0101 = initial data is valid on the 7th rising CLK edge after addresses are latched 0110 = Reserved Programmable Wait State CR0.11 0111 = Reserved 1000 = initial data is valid on the 8th rising CLK edge after addresses are latched 1001 = initial data is valid on the 9th rising CLK edge after addresses are latched 1010 = initial data is valid on the 10th rising CLK edge after addresses are latched 1011 = initial data is valid on the 11th rising CLK edge after addresses are latched 1100 = Reserved 1101 = default 1110 = Reserved 1111 = Reserved CR0.10 RDY Polarity Reserved (Not used) RDY Reserved (Not used) Reserved Reserved RDY Function Burst Wrap Around 0 = RDY signal is active low 1 = RDY signal is active high (Default) 0 = Reserved 1 = Reserved (Default) 0 = RDY active one clock cycle before data 1 = RDY active with data (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved (Default) 1 = Reserved 0 = RDY (Default) 1 = Reserved 0 = No Wrap Around Burst 1 = Wrap Around Burst (Default) 000 = Continuous (Default) 010 = 8-Word Linear Burst Burst Length CR0.0 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes: 1. Device will be in the Asynchronous Mode upon power-up or hardware reset. 2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default). 3. CR0.3 is ignored if in continuous read mode (no warp around). 4. A software reset command is required after reading or writing the configuration registers in order to set the device back to array read mode.
CR0.9 CR0.8 CR0.7
CR0.6 CR0.5 CR0.4
CR0.3 CR0.2 CR0.1
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5. Refer to Table 12.1 on page 85 for reading the settings and writing onto configuration registers command sequences. 6. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous settings.
7.6
Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 7.32 on page 32). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). See Table 12.1 on page 85 for command sequence details. Table 7.32 Autoselect Addresses
Description Manufacturer ID Word 00 Device ID, Word 01 Sector Lock/Unlock Word 02 Address (BA) + 00h Read Data 0001h
(BA) + 01h
227Eh 0001h = Locked, 0000h = Unlocked DQ15 - DQ8 = reserved DQ7 - Factory Lock Bit; 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit; 1 = Locked, 0 = Not Locked
(SA) + 02h
Indicator Bits Word 03
(BA) + 03h DQ5 - Handshake Bit; 1 = Reserved, 0 = Standard Handshake DQ4 & DQ3 - WP# Protection Boot Code; 00 = WP# Protects both Top Boot and Bottom Boot Sectors, DQ2 - DQ0 = reserved
Device ID, Word 0E Device ID, Word 0F
223Dh (WS512P)-1CE# (BA) + 0Eh 2242h (WS256P) 2244h (WS128P) (BA) + 0Fh 2200h
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Software Functions and Sample Code
Table 7.33 Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write Byte Address BA+AAAh BA+555h BA+AAAh Word Address BA+555h BA+2AAh BA+555h Data 0x00AAh 0x0055h 0x0090h
Table 7.34 Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle Unlock Cycle 1 Notes: 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address. Operation Write Byte Address xxxxh Word Address xxxxh Data 0x00F0h
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User's Guide for general information on Spansion Flash memory software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef volatile unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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7.7
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the configuration register (Table 7.31 on page 31). During synchronous write operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. Addresses are latched on the rising edge of AVD# pulse or rising edge of CLK or falling edge of WE#, whichever occurs first. During asynchronous write operations, addresses are latched on the rising edge of AVD# or falling edge of WE# while data is latched on the 1st rising edge of WE#, or CE# whichever comes first. Note the following: When the Embedded Program/Erase algorithm is complete, the device returns to the read mode. The system can determine the status of the Program/Erase operation. Refer to Write Operation Status on page 47 for further information. While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt will be ignored as only an erase operation can covert a 0 to a 1. For example: Old Data = 0011 New Data = 0101 Result = 0001 Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/Erase Suspend commands. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a Program/Erase operation is in progress. A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See Write Buffer Programming on page 36 when using the write buffer.
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7.7.1
Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. While the single word programming method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 12.1 on page 85 for the required bus cycles and Figure 7.3 for the flowchart. When the Embedded Program algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Figure 7.3 Single Word Program
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2
Write Program Command: Address 555h, Data A0h
Setup Command
Program Data to Address: PA, PD
Program Address (PA), Program Data (PD)
Perform Polling Algorithm
(see Write Operation Status flowchart)
Polling Status = Busy? No Yes Polling Status = completed No
Yes
Error condition (Exceeded Timing Limits)
Operation successfully completed
Operation failed
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Software Functions and Sample Code
Table 7.35 Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note: Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */
7.7.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. At this point, the system writes the number of word locations minus 1 that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: the size of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address must be the least significant address. All subsequent addresses and write buffer data must be in sequential order. The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order. After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/data pairs do no match the word count, the program buffer to flash command is ignored. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command will be programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then go busy. The Data Bar polling techniques
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should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence is ABORTED in the following ways: Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this condition). Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles.
Software Functions and Sample Code
Table 7.36 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N-1)h
Program Address Program Address
Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h
Notes: 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
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The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* A write buffer begins at addresses evenly divisible */ /* by 0x20. UINT16 i; */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i<=wc;i++) { *dst++ = *src++; /* ALL dst MUST BE in same Write Buffer */ } *( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* Example: Write Buffer Abort Reset */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x00F0; /* write buffer abort reset */
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Figure 7.4 Write Buffer Programming Operation
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2
Issue Write Buffer Load Command: Program Address Data 25h
Load Word Count to Program Program Data to Address: SA = wc
wc = number of words - 1
Yes wc = 0?
Confirm command: 29h
No Write Next Word, Decrement wc: PA data , wc = wc - 1 Perform Polling Algorithm
(see Write Operation Status flowchart)
Polling Status = Done? No No
Yes
Error?
Yes
Write Buffer Abort? No
Yes
RESET. Issue Write Buffer Abort Reset Command
FAIL. Issue reset command to return to read array mode.
PASS. Device is in read mode.
7.7.3
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. Bank address needs to be provided when writing the Program Suspend Command. After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored
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in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect on page 32 for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 47 for more information. Note: While a program operation can be suspended and resumed multiple times, a minimum delay of tPRS (Program Resume to Suspend) is required from resume to the next suspend. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.
Software Functions and Sample Code
Table 7.37 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 00B0h
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */
Table 7.38 Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 0030h
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */
7.7.4
Sector Erase
The sector erase function erases one or more sectors in the memory array (see Table 12.1 on page 85 and Figure 7.5 on page 42). The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the timeout period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (see DQ3: Sector Erase Timeout State Indicator on page 50). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status on page 47 for information on these status bits.
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Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 7.5 on page 42 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations on page 34 for parameters and timing diagrams.
Software Functions and Sample Code
Table 7.39 Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Sector Erase Command Operation Write Write Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Sector Address Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address Data 00AAh 0055h 0080h 00AAh 0055h 0030h
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA.
The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)sector_address ) */ )= )= )= )= )= = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0030; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ sector erase command */
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Figure 7.5 Sector Erase Operation
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2
Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h
Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure
No
Select Additional Sectors? Yes Write Additional Sector Addresses
* Each additional cycle must be written within tSEA timeout * Timeout resets after each additional cycle is written * The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands
No
Poll DQ3. DQ3 = 1? Yes
Yes
Last Sector Selected? No
* No limit on number of sectors * Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data
Perform Write Operation Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Device returns to reading array.
FAIL. Write reset command to return to reading array.
Notes: 1. See Table 12.1 on page 85 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timeout.
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7.7.5
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 12.1 on page 85. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. Table 12.1 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to Write Operation Status on page 47 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Software Functions and Sample Code
Table 7.40 Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command Operation Write Write Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0080h 00AAh 0055h 0010h
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x000 )
= = = = = =
0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0010;
/* /* /* /* /* /*
write write write write write write
unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ chip erase command */
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7.7.6
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written after the tSEA time-out period has expired and during the sector erase operation, the device requires a minimum of tESL (erase suspend latency) to suspend the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 7.47 on page 51 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Note: While an erase operation can be suspended and resumed multiple times, a minimum delay of tERS (Erase Resume to Suspend) is required from resume to the next suspend. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to Write Buffer Programming on page 36 and Autoselect on page 32 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Software Functions and Sample Code
Table 7.41 Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 00B0h
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */
Table 7.42 Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 0030h
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command /* The flash needs adequate time in the resume state */ */
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7.7.7
Accelerated Program/Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the ACC function. This method is faster than the standard chip program and erase command sequences. The accelerated program and erase functions must not be used more than 10 times per sector. In addition, accelerated program and erase should be performed at room temperature (25C 10C). If the system asserts VHH on this input, the device automatically enters the accelerated mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Sectors must be unlocked prior to raising ACC to VHH. The ACC pin must not be at VHH for operations other than accelerated programming accelerated erase, or device damage may result. The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. ACC locks all sector if set to VIL; ACC should be set to VIH for all other conditions.
7.7.8
Unlock Bypass
The unlock bypass feature allows the system to primarily program faster than using the standard program command sequence, and it is not intended for use during erase. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The erase command sequences are four cycles in length instead of six cycles. Table 12.1 on page 85 shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Refer to Erase/Program Timing on page 76 for parameters, and Figure 11.15 on page 77 and Figure 11.16 on page 78 for timing diagrams.
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Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low Level Driver User's Guide (available soon on www.spansion.com) for general information on Spansion Flash memory software development guidelines. Table 7.43 Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle 1 2 3 Description Unlock Unlock Entry Command Operation Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0020h
/* Example: Unlock Bypass Entry Command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock *( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock /* At this point, programming only takes two write cycles. /* Once you enter Unlock Bypass Mode, do a series of like /* operations (programming or sector erase) and then exit /* Unlock Bypass Mode before beginning a different type of /* operations.
cycle 1 cycle 2 bypass command */ */ */ */ */
*/ */ */
Table 7.44 Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd) Cycle
1 2
Description
Program Setup Command Program Command
Operation
Write Write
Byte Address
Base + xxxh Program Address
Word Address
Base +xxxh Program Address
Data
00A0h Program Data
/* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; *( (UINT16 *)pa ) = data; /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */
/* write program setup command /* write data to be programmed
*/ */
Table 7.45 Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle 1 2 Description Reset Cycle 1 Reset Cycle 2 Operation Write Write Byte Address Base + xxxh Base + xxxh Word Address Base +xxxh Base +xxxh Data 0090h 0000h
/* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000;
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7.7.9
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer when write buffer programming is used. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. Similarly, attempting to program 1 over a 0 does not return valid Date# information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ1 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ1 may be still invalid. Valid data on DQ7-DQ1 appears on successive read cycles. See the following for more information: Table 7.47 on page 51, shows the outputs for Data# Polling on DQ7. Figure 7.6 on page 48, shows the Data# Polling algorithm; and Figure 11.19 on page 80, shows the Data# Polling timing diagram.
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Figure 7.6 Write Operation Status Flowchart
START
Read 1
(Note 6) DQ7=valid data? NO
YES
Erase Operation Complete
Read 1 DQ5=1? NO
YES
Read 2
YES Read3= valid data? NO
YES
Write Buffer Programming?
Read 2
Read 3 Program Operation Failed YES
Programming Operation?
NO Read 3 Device BUSY, Re-Poll
NO (Note 3) (Note 1) DQ6 toggling? YES TIMEOUT (Note 1) DQ6 toggling? NO (Note 2) Device BUSY, Re-Poll Read 2 DQ2 toggling? NO YES DEVICE ERROR (Note 5)
(Note 4) Read3 DQ1=1?
YES
NO
NO
YES
Device BUSY, Re-Poll Erase Operation Complete Device in Erase/Suspend Mode
Read 3
Read3 DQ1=1 AND DQ7 Valid Data?
YES
Write Buffer Operation Failed
NO
Device BUSY, Re-Poll
Notes: 1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3. May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4. Write buffer error if DQ1 of last read =1. 5. Invalid state, use RESET command to exit operation. 6. Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. Data polling algorithm valid for all operations except advanced sector protection.
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See the following for additional information: Figure 7.6 on page 48, Figure 11.20 on page 80, and Table 7.46 on page 49 and Table 7.47 on page 51. Toggle Bit I on DQ6 requires Read address to be relatched by toggling AVD# for each reading cycle.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 7.46 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 7.6 on page 48, DQ6: Toggle Bit I on page 49, and Figures 11.19-11.22. Read address has to be relatched by toggling AVD# for each reading cycle. Table 7.46 DQ6 and DQ2 Indications
If device is programming, and the system reads at any address at the bank being programmed at an address within a sector selected for erasure, actively erasing, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, erase suspended, at an address within sectors not selected for erasure, programming in erase suspend at any address at the bank being programmed returns array data, toggles, returns array data. The system can read from any sector not selected for erasure. is not applicable. toggles, does not toggle, does not toggle. toggles. then DQ6 toggles, toggles, and DQ2 does not toggle. also toggles.
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Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 7.6 on page 48 for more details. Note: When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and DQ2 toggle between high and low states in a series of consecutive and contiguous status read cycles. In order for this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. If it is not possible to temporarily prevent reads to other memory banks, then it is recommended to use the DQ7 status bit as the alternative method of determining the active or inactive status of the write operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device does not output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits that were correctly requested to be changed from 1 to 0 are programmed. Attempting to program a 0 to a 1 is masked during the programming operation. Under valid DQ5 conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 7.47 on page 51 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details.
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Table 7.47 Write Operation Status
Status Standard Mode Program Suspend Mode (Note 3) Embedded Program Algorithm Embedded Erase Algorithm Reading within Program Suspended Sector Reading within Non-Program Suspended Sector Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector DQ7 (Note 2) DQ7# 0 INVALID (Not Allowed) Data 1 Data DQ7# DQ7# DQ7# DQ7# DQ6 Toggle Toggle INVALID (Not Allowed) Data No toggle Data Toggle Toggle Toggle Toggle DQ5 (Note 1) 0 0 INVALID (Not Allowed) Data 0 Data 0 0 1 0 DQ3 N/A 1 INVALID (Not Allowed) Data N/A Data N/A N/A N/A N/A DQ2 (Note 2) No toggle Toggle INVALID (Not Allowed) Data Toggle Data N/A N/A N/A N/A DQ1 (Note 4) 0 N/A INVALID (Not Allowed) Data N/A Data N/A 0 0 1
Erase Suspend Mode
Erase-Suspend-Program Write to Buffer (Note 5) BUSY State Exceeded Timing Limits ABORT State
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. Data are invalid for addresses in a Program Suspended sector. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
7.8
Simultaneous Read/Program or Erase
The simultaneous read/program or erase feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 11.25 on page 83 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to DC Characteristics on page 67 for read-while-program and read-while-erase current specification.
7.9
Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Table 6.2 on page 17 and Table 6.3 on page 18 indicate the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to uniquely select a sector. ICC2 in DC Characteristics on page 67 represents the active current specification for the write mode. AC Characteristics-Synchronous and AC Characteristics-Asynchronous contain timing specification tables and timing diagrams for write operations.
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7.10
Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY pin which is a dedicated output and is controlled by CE#.
7.11
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. See Figure 11.5 on page 69 and Figure 11.14 on page 75 for timing diagrams.
7.12
Software Reset
Software reset is part of the command set (see Table 12.1 on page 85) that also returns the device to array read mode and must be used for the following conditions: to exit Autoselect mode when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed exit sector lock/unlock operation. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode. after any aborted operations Exiting Read Configuration Registration Mode
Software Functions and Sample Code
Table 7.48 Reset (LLD Function = lld_ResetCmd)
Cycle Reset Command Note: Base = Base Address. Operation Write Byte Address Base + xxxh Word Address Base + xxxh Data 00F0h
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command: This command resets the banks to the read and address bits are ignored. Reset commands are ignored once erasure has begun until the operation is complete. Once programming begins, the device ignores reset commands until the operation is complete The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode.
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If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command may be also written during an Autoselect command sequence. If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details].
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8. Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1 on page 54. Figure 8.1 Advanced Sector Protection/Unprotection
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = VIL (All sectors locked)
Password Method
(DQ2)
Persistent Method
(DQ1)
(All boot sectors locked)
WP# = VIL
64-bit Password
(One Time Protect)
PPB Lock Bit 0 = PPBs Locked
1,2,3
1 = PPBs Unlocked
1. Bit is volatile, and defaults to "1" on reset. 2. Programming to "0" locks all PPBs to their current state. 3. Once programmed to "0", requires hardware reset to unlock.
Memory Array
Sector 0 Sector 1 Sector 2
Persistent Protection Bit (PPB)5, 6
PPB 0 PPB 1 PPB 2
Dynamic Protection Bit (DYB)7, 8, 9
DYB 0 DYB 1 DYB 2
Sector N-2 Sector N-1 Sector N
4
PPB N-2 PPB N-1 PPB N
5. 0 = Sector Protected, 1 = Sector Unprotected. 6. PPBs programmed individually, but cleared collectively
DYB N-2 DYB N-1 DYB N
7. 0 = Sector Protected, 1 = Sector Unprotected. 8. DYB bits are only effective for sectors that not protected via PPB locking mechanism. 9. Volatile Bits: defaults to unprotected after power up.
4. N = Highest Address Sector.
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8.1
Advanced Sector Protection Software Examples
Table 8.1 Sector Protection Schemes
Unique Device PPB Lock Bit 0 = locked 1 = unlocked Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector 0 0 0 0 1 1 1 1 Sector PPB 0 = protected 1 = unprotected 0 0 1 1 0 0 1 1 Sector DYB 0 = protected 1 = unprotected x x 1 0 x x 0 1
Sector Protection Status Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected
Table 8.1 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector.
8.2
Lock Register
The Lock Register consists of 4 bits. The Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, Password Protection Mode Lock Bit is DQ2, Persistent Sector Protection OTP bit is DQ3. If DQ0 is `0', it means that the Customer Secured Silicon area is locked and if DQ0 is `1', it means that it is unlocked. When DQ2 is set to `1' and DQ1 is set to `0', the device can only be used in the Persistent Protection Mode. When the device is set to Password Protection Mode, DQ1 is required to be set to `1' and DQ2 is required to be set to `0'. DQ3 is programmed in the Spansion factory. When the device is programmed to disable all PPB erase command, DQ3 outputs a `0', when the lock register bits are read. Similarly, if the device is programmed to enable all PPB erase command, DQ3 outputs a `1' when the lock register bits are read. Likewise the DQ4 bit is also programmed in the Spansion Factory. DQ4 is the bit which indicates whether Volatile Sector Protection Bit (DYB) is protected or not after boot-up. When the device is programmed to set all Volatile Sector Protection Bit protected after power-up, DQ4 outputs a `0' when the lock register bits are read. Similarly, when the device is programmed to set all Volatile Sector Protection Bit unprotected after power-up, DQ4 outputs a `1'. Each of these bits in the lock register are non-volatile. DQ15DQ5 are reserved and will be 1's. For programming lock register bits refer to Table 12.2 on page 87. Table 8.2 Lock Register
DQ15-5 DQ4 DQ3 PPB One Time Programmable Bit 1's Reserved (default = 1) 0 = All PPB Erase Command disabled 1 = All PPB Erase Command enabled Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Secured Silicon Sector Protection Bit DQ2 DQ1 DQ0
Notes: 1. If the password mode is chosen, the password must be programmed and verified before setting the corresponding lock register bit (DQ2). Failing to program and verifying the password prior to setting lock register (DQ2), causes all sectors to lock out. 2. It is recommended a sector protection method to be chosen by programming DQ1 or DQ2 prior to shipment. 3. After the Lock Register Bits Command Set Entry sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. Simultaneous operation is only valid as long as lock register program command is not executed. 4. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 5. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. 6. During erase/program suspend, ASP entry commands are not allowed. 7. Data Polling can be done immediately after the lock register programming command sequence (no delay required). Note that status polling can be done only in bank 0 8. Reads from other banks (simultaneous operation) are not allowed during lock register programming. This restriction applies to both synchronous and asynchronous read operations.
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After selecting a sector protection method, each sector can operate in any of the following three states: 1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. 2. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Sections 8.3-8.6.
8.3
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring.
Notes:
1. Each PPB is individually programmed and all are erased in parallel. 2. While programming PPB for a sector, array data can not be read from any other banks. 3. Entry command disables reads and writes for the bank selected. 4. Reads within that bank return the PPB status for that sector. 5. Reads from other banks are allowed while program/erase is not allowed. 6. All Reads must be performed using the Asynchronous mode. 7. The specific sector address (Amax-A14) are written at the same time as the program command. 8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. 9. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 10. The PPB Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 11. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 8.2 on page 57. 12. During PPB program / erase data polling can be done synchronously. 13. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode.
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Figure 8.2 PPB Program/Erase Algorithm
Enter PPB Command Set. Addr = BA
Program PPB Bit. Addr = SA0
Read Byte Twice Addr = SA0
DQ6 = Toggle? Yes No
No
DQ5 = 1? Yes Read Byte Twice Addr = SA0 Wait 500 s
DQ6 = Toggle? Yes
No
Read Byte. Addr = SA
No
DQ0 = '1' (Erase) '0' (Pgm.)? Yes
FAIL
End
PASS
Exit PPB Command Set
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8.4
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
Notes
1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When the parts are first shipped, the PPBs are cleared (erased to 1). 2. The default state of DYB is unprotected after power up and all sectors can be modified depending on the status of PPB bit for that sector, (erased to 1). Then the sectors can be modified depending upon the PPB state of that sector (see Table 8.1 on page 55). 3. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 4. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 5. Data polling is not available for DYB program / erase. 6. DYB read data can be done synchronously. 7. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode.
8.5
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to 0), it locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings.
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8.6
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. If the password mode is chosen, the password must be programmed and verified before setting the corresponding lock register bit (DQ2). Failing to program and verifying the password prior to setting lock register (DQ2), causes all sectors to lock out. 2. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. 3. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0. 4. The password is all 1s when shipped from the factory. 5. All 64-bit password combinations are valid as a password. 6. There is no means to verify what the password is after it is set. 7. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 8. The Password Mode Lock Bit is not erasable. 9. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. 10. The exact password must be entered in order for the unlocking function to occur. 11. The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 12. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 13. Password verification is only allowed during the password programming operation. 14. All further commands to the password region are disabled and all operations are ignored. 15. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 16. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 17. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 18. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 19. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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Figure 8.3 Lock Register Program Algorithm
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2
Write Enter Lock Register Command: Address 555h, Data 40h
Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD
XXXh = Address don't care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once.
Perform Polling Algorithm
(see Write Operation Status flowchart)
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array.
FAIL. Write rest command to return to reading array.
8.7
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control: When WP# is at VIL, the four outermost sectors (including Secured Silicon Area) are locked. When ACC is at VIL, all sectors (including Secured Silicon Area) are locked. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
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8.7.1
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. Table 8.3 S29WS512P Sector Protection
Dual Boot Configuration Bank 0 Bank 1-7 Bank 8-14 Bank 15 SA000-SA003 WP# Protected No Sector WP# Protection No Sector WP# Protection SA514-SA517 WP# Protected
Table 8.4 S29WS256P Sector Protection
Dual Boot Configuration Bank 0 Bank 1-7 Bank 8-14 Bank 15 SA000-SA003 WP# Protected No Sector WP# Protection No Sector WP# Protection SA258-SA261 WP# Protected
Table 8.5 S29WS128P Sector Protection
Dual Boot Configuration Bank 0 Bank 1-7 Bank 8-14 Bank 15 SA000-SA003 WP# Protected No Sector WP# Protection No Sector WP# Protection SA130-SA133 WP# Protected
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the outermost boot sectors, as well as Secured Silicon Area. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution
8.7.2
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are disabled and hence all sectors (including the Secured Silicon Area) are protected.
8.7.3
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
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8.7.4
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.7.5
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
9. Power Conservation Modes
9.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC Characteristics on page 67 represents the standby current specification
9.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption only while in asynchronous main array read mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in DC Characteristics on page 67 represents the automatic sleep mode current specification.
9.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
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10. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. Please note the following general conditions: While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads can be performed in the Asynchronous or Synchronous mode. Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h. Reads outside of sector 0 return memory array data. Continuous burst read past the maximum address is undefined. Sector 0 is remapped from memory array to Secured Silicon Sector array. Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. Table 10.1 Secured Silicon Sector Addresses
Sector Customer Factory Sector Size 128 words 128 words Address Range 000080h-0000FFh 000000h-00007Fh
10.1
Factory Secured Silicon Sector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: A random, 8 Word secure ESN only within the Factory Secured Silicon Sector Customer code within the Customer Secured Silicon Sector through the Spansion(R) programming service. Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services.
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10.2
Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to 1. The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is available. Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0.
10.3
Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See Command Definition Table [Secured Silicon Sector Command Table, Appendix Table 12.1 on page 85 for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read customer and factory Secured Silicon areas Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User's Guide (available soon on www.spansion.com) for general information on Spansion Flash memory software development guidelines. Table 10.2 Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle Note: Base = Base Address. Operation Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0088h
/* Example: Secured Silicon Sector *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) = */
Entry Command */ = 0x00AA; /* write unlock cycle 1 */ = 0x0055; /* write unlock cycle 2 */ 0x0088; /* write Secured Silicon Sector Entry Cmd
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Table 10.3 Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note: Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
/* Once in the Secured Silicon Sector mode, you program */ /* words using the programming algorithm. */
Table 10.4 Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle 3 Exit Cycle 4 Note: Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Any address Word Address Base + 555h Base + 2AAh Base + 555h Any address Data 00AAh 0055h 0090h 0000h
/* Example: Secured Silicon Sector Exit Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write Secured Silicon Sector Exit cycle 3 */ *( (UINT16 *)base_addr + 0x000 ) = 0x0000; /* write Secured Silicon Sector Exit cycle 4 */
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11. Electrical Specifications
11.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) VCC (Note 1) ACC (Note 2) Output Short Circuit Current (Note 3) -65C to +150C -65C to +125C -0.5 V to + 2.5 V -0.5 V to +2.5 V -0.5 V to +9.5 V 100 mA
Notes: 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2. 2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 11.1 Maximum Negative Overshoot Waveform 20 ns +0.8 V -0.5 V -2.0 V 20 ns Figure 11.2 Maximum Positive Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 20 ns
11.2
Operating Ranges
Wireless (I) Devices Supply Voltages Ambient Temperature (TA) VCC Supply Voltages -25C to +85C +1.70 V to +1.95 V
Note Operating ranges define those limits between which the functionality of the device is guaranteed.
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11.3
DC Characteristics
CMOS Compatible
Table 11.1 CMOS Compatible
Parameter ILI ILO Description Input Load Current Output Leakage Current Test Conditions (Note 1) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax 54 Mhz CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 66 Mhz 80 Mhz 104 Mhz 54 Mhz CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32 66 Mhz 80 Mhz 104 Mhz 54 Mhz 66 Mhz 80 Mhz 104 Mhz 54 Mhz CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous 66 Mhz 80 Mhz 104 Mhz 10 MHz ICC1 VCC Active Asynchronous Read Current (Note 2) CE# = VIL, OE# = VIH, WE# = VIH 5 MHz 1 MHz ICC2 VCC Active Program/Erase Current (Note 2) VCC Standby Current (Note 3) VCC Reset Current VCC Active Current (Read While Program/Erase) VCC Sleep Current VCC Active Page Read Current Accelerated Program Current (Note 4) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage IOL = 100 A, VCC = VCC min IOH = -100 A, VCC = VCC min VCC - 0.1 8.5 9.5 1.4 CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH, ACC = VIH, 5 MHz CE# = VIL, OE# = VIH, (VCCQ or VSSQ biased at Rail to Rail for all inputs) OE# = VIH, 8 word Page Read CE# = VIL, OE# = VIH, VACC = 9.5 V VACC VCC -0.2 VCC - 0.4 VACC VCC VACC VCC 40 20 10 1 20 1 20 30 40 5 10 7 15 34 37 41 TBA 80 40 20 5 60 5 70 60 60 40 15 10 20 0.4 VCC + 0.4 0.1 V V V V 33 36 40 TBA 39 43 48 32 35 39 TBA 38 42 47 32 35 39 TBA 37 41 46 Min Typ Max 1 1 37 41 46 Unit A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A mA A A A mA A mA mA mA V
11.3.1
ICC3 ICC4 ICC5 ICC6 ICC7 IACC VIL VIH VOL VOH VHH VLKO
Notes: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 4. Total current during accelerated programming is the sum of VACC and VCC currents. 5. VCCQ = VCC during all ICC measurements. 6. VIH = VCC 0.2V and VIL 0.1V
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11.4
Test Conditions
Figure 11.3 Test Setup Device Under Test CL
Table 11.2 Test Specifications
Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels All Speed Options 30 1.0 - 1.50 0.0-VCC VCC/2 VCC/2 Unit pF ns V V V
11.5
Key to Switching Waveforms
Waveform Inputs Steady Outputs
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
11.6
Switching Waveforms
Figure 11.4 Input Waveforms and Measurement Levels
All Inputs and Outputs VCC 0.0 V Input VCC/2 Measurement Level VCC/2 Output
Table 11.3 VCC Power-up
Parameter tVCS tRH Description VCC Setup Time Time between RESET# (high) and CE# (low) Test Setup Min Min Time 30 200 Unit s ns
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11.7
Power-up/Initialization
Power supply must reach its minimum voltage range before applying/removing the next supply voltage. RESET# must ramp down to VIL level before VCC/VCCQ can start ramp up. VCC and VCCQ must be ramped simultaneously for proper power-up. Figure 11.5 VCC Power-up Diagram
tVCS VCC min VCC/ VCCQ VIH RESET# tRH CE#
11.8
CLK Characterization
Parameter Description Max fCLK CLK Frequency Min 54 MHz 54 66 MHz 66 80 MHz 80 60 KHz in 8 word Burst, 120 KHz in 16 word Burst, 250 KHz in 32 word Burst, 1 MHz in Continuous Mode 18.5 15.1 12.5 0.45 tCLK 0.55 tCLK 3.0 3.0 2.5 1.5 ns 9.62 ns ns 104 MHz 104 Unit MHz
tCLK tCL/tCH tCR tCF
CLK Period CLK Low/High Time
Min Min Max
CLK Rise Time Max CLK Fall Time
Figure 11.6 CLK Characterization
tCLK tCH tCL
CLK
tCR
tCF
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11.9
AC Characteristics
Synchronous/Burst Read
Parameter JEDEC Standard tIACC tBACC tACS tACH tBDH tRDY tOE tCEZ tOEZ tCES tRACC tCAS tAVC tAVD Description Synchronous Access Time Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time Chip Enable to RDY Active Output Enable to RDY Low Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK Ready Access Time from CLK CE# Setup Time to AVD# AVD# Low to CLK Setup Time AVD# Pulse Max Max Min Min Min Max Max Max Max Min Max Min Min Min 13.5 11.2 0 6 tCLK 13.5 10 10 11.2 10 10 6 9 7.6 13.5 5 6 4 54 MHz 66 MHz 80 MHz 104 MHz Unit ns 7.6 3.5 5 2 ns ns ns ns ns 9 10 10 7.6 7 7 ns ns ns ns ns ns ns ns
11.9.1
(WS-1) * tCK + tBACC 11.2 4 6 3 10 9 4 5 3
Notes: 1. Addresses are latched on the rising edge of CLK 2. Synchronous Access Time is calculated using the formula (#of WS - 1)*(clock period) + (tBACC or Clock to Out)
Table 11.4 Non-Continuous Burst Mode with Wrap Around Burst Mode.
Max Frequency Frequency 27 MHz 27 MHz < Frequency 40 MHz 40 MHz < Frequency 54 MHz 54 MHz < Frequency 66 MHz 66 MHz < Frequency 80 MHz 80 MHz < Frequency 95 MHz 95 MHz < Frequency 104 MHz Wait State Requirement 3 4 5 6 7 8 11
Table 11.5 Continuous Burst Mode with No Wrap Around Burst Mode.
Max Frequency Frequency 27 MHz 27 MHz < Frequency 40 MHz 40 MHz < Frequency 54 MHz 54 MHz < Frequency 66 MHz 67 MHz < Frequency 80 MHz 80 MHz < Frequency 95 MHz 95 MHz < Frequency 104 MHz Wait State Requirement 3 4 6 7 8 9 11
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Figure 11.7 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around
1 CLK tCES CE# tAVC AVD# tACS tBACC Data tACH Address
AC DC
2
3
4
5
6
7
7 cycles for initial access is shown as an illustration.
tCLKH tCLKL
tAVD
tCLK
tCEZ
tOEZ
High-Z
tIACC
DD
DE
DB
OE# tRDY RDY
Hi-Z
tBDH tOE tRACC
tCEZ
High-Z
Notes: 1. Figure shows for illustration the total number of wait states set to seven cycles. 2. The device is configured synchronous single data rate mode and RDY active with data. 3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the DQ(15:0) pins to Hi-Z.
Figure 11.8 8-word Linear Single Data Read Synchronous Burst without Wrap Around
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Ac 7? cycles for initial access shown.
2
3
4
5
6
7
tAVD
tACH Data tIACC OE# tRDY RDY
Hi-Z DC DD
tBACC
DE
DF
D10
D13
tBDH tRACC
tOE
tRACC
tRDYS
Notes: 1. Figure shows for illustration the total number of wait states set to seven cycles. 2. The device is configured synchronous single data rate mode and RDY active with data. 3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the DQ(15:0) pins to HI-Z.
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11.9.2
Asynchronous Mode Read
Parameter JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS tPACC tCEZ Description Access Time from CE# Low Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Read Output Enable Hold Time Output Enable to High Z CE# Setup Time to AVD# Intra Page Access Time Chip Enable to High Z Toggle and Data# Polling Max Max Min Min Min Max Min Min Max Min Max Max Asynchronous 83 80 7.5 6 4 13.5 0 4 7.6 0 20 7.6 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Figure 11.9 Asynchronous Read Mode (AVD# Toggling - Case 1)
CLK
CE#
VIL or VIH
tCEZ
AVD#
tAVDP
OE#
tWEA tOEH
tOE
WE#
tCE RD
tOEZ
DQ15-DQ0
tAAVDS Amax-A0 tRDY VA
tAAVDH
tCEZ
RDY
Hi-Z
Hi-Z
Notes: 1. Valid Address and AVD# Transition occur before CE# is driven Low. 2. VA = Valid Read Address, RD = Read Data.
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Figure 11.10 Asynchronous Read Mode (AVD# Toggling - Case 2)
CLK
CE#
VIL or VIH
tCAS
tCEZ
AVD#
tAVDP
tOE
OE#
tWEA tOEH
WE#
tOEZ
DQ15-DQ0 tAAVDS Amax-A0
tRDY
tAAVDH
RD
VA tACC
tCEZ
RDY
Hi-Z
Hi-Z
Notes: 1. AVD# Transition occurs after CE# is driven to Low and Valid Address Transition occurs before AVD# is driven to Low. 2. VA = Valid Read Address, RD = Read Data.
Figure 11.11 Asynchronous Read Mode (AVD# Toggling - Case 3)
CLK
CE#
VIL or VIH
tCAS
tCEZ
AVD#
tAVDP
tOE
OE#
tWEA tOEH
WE#
tOEZ
DQ15-DQ0 tAAVDS Amax-A0
tRDY
tAAVDH
RD
VA tACC
tCEZ
RDY
Hi-Z
Hi-Z
Notes: 1. AVD# Transition occurs after CE# is driven to Low and AVD# is driven low before Valid Address Transition. 2. VA = Valid Read Address, RD = Read Data.
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Figure 11.12 Asynchronous Read Mode (AVD# tied to CE#)
CLK
CE# AVD# OE# tOE tOEH
VIL or VIH
tRC tCEZ
WE#
tWEA
tCE RD tACC
tOEZ
DQ15-DQ0
Amax-A0
VA tRDY tCEZ Hi-Z
RDY Hi-Z
Notes: 1. AVD# is tied to CE# 2. VA = Valid Read Address, RD = Read Data.
Figure 11.13 Asynchronous Page Mode Read
Amax-A3
Page
A2-A0
A0
tACC
A1
tPACC
A2
tPACC tPACC
Ax
Data Bus CE# OE# AVD#
Note RA = Read Address, RD = Read Data.
D0
D1
Dx
D7
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11.9.3
Hardware Reset (RESET#)
Table 11.6 Hardware Reset
Parameter JEDEC Std tRP tRH Description RESET# Pulse Width Reset High Time Before Read Min Min All Speed Options 30 200
Unit s ns
Figure 11.14 Reset Timings
CE#, OE# tRH RESET# tRP
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11.9.4
Erase/Program Timing
Parameter JEDEC tAVAV tAVWL Standard tWC tAS Write Cycle Time (Note 1) Synchronous Address Setup Time (Note 2) Asynchronous Synchronous tWLAX tAH tAVDP tDVWH tWHDX tGHWL tDS tDH tGHWL tCAS tWHEH tWLWH tWHWL tCH tWP tWPH tSR/W tVID tVIDS tELWL tCS tAVSW tAVHW tAVSC tAVHC tSEA tESL tPSL tASP tPSP Address Hold Time (Note 2) Asynchronous AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Setup Time to CLK AVD# Hold Time to CLK Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Erase within a Protected Sector Toggle Time During Programming Within a Protected Sector Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Max Typ Typ 5 5 5 5 50 40 40 0 0 Min 7 7 6 20 0 0 0 0 25 20 0 500 1 4 4 4 5 5 3 3 6 5 ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns s s s s s Min 6 7 6 7 6 6 6 5 ns Description Min 5 5 54 MHz 66 MHz 60 5 3.5 ns 80 MHz 104 MHz Unit ns
Notes 1. Sampled, not 100% tested. 2. In programming operations, addresses are latched on the active edge of CLK for programming synchronously or rising edge of AVD# for programming asynchronously. 3. See the Erase and Programming Performance on page 84 section for more information. Does not include the preprogramming time.
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Figure 11.15 Asynchronous Program Operation Timings
VIH
Program Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 555h tAH PA VA
In Progress
VA
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE# tWP WE# tCS tWPH tWC tVCS VCC
tCH
Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. In progress and complete refer to status of program operation. 3. CLK can be either VIL or VIH.
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Figure 11.16 Synchronous Program Operation Timings
Program Command Sequence (last two cycles) tAVHC CLK tAS tAH tAVSC AVD# tAVDP Addresses 555h PA VA
In Progress
Read Status Data
VA
Data tCAS CE#
A0h tDH
PD tDS
Complete
tAVHW
OE#
tAVSW tWP
tCH
WE# tWPH tWC
tWC tVCS VCC
Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. In progress and complete refer to status of program operation. 3. Addresses are latched on the first rising edge of CLK.
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Figure 11.17 Chip/Sector Erase Command Sequence
Erase Command Sequence (last two cycles) Read Status Data
VIH
CLK
VIL
tAVDP AVD# tAS Addresses 2AAh tAH SA
555h for chip erase 10h for chip erase
VA
In Progress
VA
Data
55h
30h tDS tDH
Complete
CE#
OE# tWP WE# tCS tVCS VCC
Note: SA is the sector address for Sector Erase.
tCH
tWHWH2 tWPH tWC
Figure 11.18 Accelerated Unlock Bypass Programming Timing
CE#
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VHH
1 s
tVIDS
VIL or VIH
Note: Use setup and hold times from conventional program operation.
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Figure 11.19 Data# Polling Timings (During Embedded Algorithm)
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses
High Z
tCEZ
tOE
tOEZ
VA
VA
High Z
Data
Status Data
Status Data
Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data.
Figure 11.20 Toggle Bit Timings (During Embedded Algorithm)
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses
High Z
tCEZ
tOE
tOEZ
VA
VA
High Z
Data
Status Data
Status Data
Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
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Figure 11.21 Synchronous Data Polling Timings/Toggle Bit Timings
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle before data.
Figure 11.22 DQ2 vs. DQ6
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
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Figure 11.23 Latency with Boundary Crossing
Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
Address (hex) 7C CLK
7D
7E
7F
7F
80
81
82
83
AVD#
(stays high) tRACC tRACC
latency
RDY(Note 1) tRACC RDY(Note 2)
latency
tRACC
Data
D124
D125
D126
D127
Invalid
D128
D129
D130
OE#, CE#
(stays low)
Notes: 1. RDY active with data (CR0.8 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (CR0.8 = 1 in the Configuration Register). 3. Figure shows the device not crossing a bank in the process of performing an erase or program.
Figure 11.24 Wait State Configuration Register Setup
Data D0 D1
AVD#
total number of clock cycles following addresses being latched
Rising edge of next clock cycle following last wait state triggers next burst data
OE# 1 CLK 2 3 4 5 6 7
0
1
2
4
6
8
10
12
13
14
Total number of clock edges following addresses being latched
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Table 11.7 Example of Programmable Wait States
CR1.0 CR0.13 CR0.12 0000 = initial data is valid on the 2rd rising CLK edge after addresses are latched 0001 =initial data is valid on the 3rd rising CLK edge after addresses are latched 0010 = initial data is valid on the 4th rising CLK edge after addresses are latched 0011 = initial data is valid on the 5th rising CLK edge after addresses are latched 0100 = initial data is valid on the 6th rising CLK edge after addresses are latched 0101 = initial data is valid on the 7th rising CLK edge after addresses are latched 0110 = Reserved Programmable Wait State CR0.11 0111 = Reserved 1000 = initial data is valid on the 8th rising CLK edge after addresses are latched 1001 = initial data is valid on the 9th rising CLK edge after addresses are latched 101 1= initial data is valid on the 10th rising CLK edge after addresses are latched . . 1101 = Reserved 1110 = Reserved 1111 = Reserved
Figure 11.25 Back-to-Back Read/Write Cycle Timings
Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence
tWC
tRC
tRC
tWC
CE#
OE# tOE tOEH WE# tWPH tWP tDS tDH Data
PD/30h RD
tGHWL
tACC
tOEZ tOEH
RD AAh
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy bank. The system should read status twice to ensure valid information.
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11.10 Erase and Programming Performance
Parameter 64 Kword Sector Erase Time 16 Kword VCC 0.35 78.4 (WS128P) Chip Erase Time VCC VCC ACC Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time VCC ACC VCC ACC 155.2 (WS256P) 308.8 (WS512P) 40 24 9.4 6 300 192 50.4 (WS128P) VCC Chip Programming Time (using 32 word buffer) ACC 100.8 (WS256P) 201.6 (WS512P) 33.6 (WS128P) 67.2 (WS256P) 134.4 (WS512P) Erase Suspend/Erase Resume (tERS) Program Suspend/Program Resume (tPRS) 40 40 Single Word Programming Time 1.75 154 (WS128P) 308 (WS256P) 616 (WS512P) 400 s 240 94 60 s 3000 1920 157.3 (WS128P) 314.6 (WS256P) 1008 (WS512P) s 100.7 (WS128P) 201.3 (WS256P) 402.6 (WS512P) s s Excludes system level overhead (Note 4) Excludes system level overhead (Note 4) s VCC Typ (Note 1) 0.6 Max (Note 2) 3.0 s Unit Comments Excludes 00h programming prior to erasure (Note 3)
Notes: 1. Typical program and erase values are measured at TC = 25C, 1.8 V VCC, 10,000 cycles using checkerboard patterns. Sampled, but not 100% tested. 2. Under worst case conditions of 90C, VCC = 1.70 V, 100,000 cycles. 3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12.1 on page 85 and Table 12.2 on page 87 for further information on command definitions.
11.10.1
BGA Ball Capacitance
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Setup VIN = 0 VOUT = 0 Typ 2 2 Max 10 10 Unit pF pF
Notes 1. Sampled, not 100% tested. 2. Test conditions tA - 25C; f = 1.0 MHz
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12. Appendix
This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see Additional Resources on page 15, or explore the Web at www.spansion.com. Table 12.1 Memory Array Commands
Bus Cycles (Note 1 - 6) Cycles First Addr 1 1 Manufacturer ID Autoselect (9) 4 RA XXX 555 Data (19) RD F0 AA 2AA 55 (BA) 555 (BA) 555 (BA) 555 (SA) 555 555 SA 90 (BA) X00 (BA) X01 (BA) X03 (SA) X02 PA SA 0001 (BA)X 0E (BA) X0F Second Addr Data (19) Third Addr Data (19) Fourth Addr Data (19) Fifth Addr Data (19) Sixth Addr Data (19)
Command Sequence (Notes) Asynchronous Read (7) Reset (8)
Device ID (10)
6
555
AA
2AA
55
90
227E
(10)
(10)
Indicator Bits Sector Unlock/Lock Verify (11)
4
555
AA
2AA
55
90
(12) 0000/ 0001 Data WC PA (20) PD WBL PD
4 4 6 1 3 6 6 1 1 5 4
555 555 555 SA 555 555 555 BA BA 555 555 (BA) 55 555 XX XX XX XX XX
AA AA AA 29 AA AA AA B0 30 AA AA
2AA 2AA 2AA
55 55 55
90 A0 25
Single word Write Buffer to Flash Program (17) Program Buffer to Flash Write to Buffer Abort Reset (12) Chip Erase Sector Erase Program/Erase Suspend (15) Program/Erase Resume (16) Set Configuration Register (21) Read Configuration Register
2AA 2AA 2AA
55 55 55
555 555 555
F0 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30
2AA 2AA
55 55
555 555
D0 C6
X00 X0 (0 or 1)
CR0 CR (0 or 1)
X01
CR1
CFI Query (17) Unlock Bypass Entry (18) Unlock Bypass Program (13, 14) Unlock Bypass Mode Unlock Bypass Sector Erase (13, 14) Unlock Bypass Erase (13, 14) Unlock Bypass CFI (13, 14) Unlock Bypass Reset
1 3 2 2 2 1 2
98 AA A0 80 80 98 90 XXX 00 2AA PA SA XXX 55 PD 30 10 555 20
Legend X = Don't care RA = Read Address RD = Read Data PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. Notes 1. See Table 7.1 on page 19 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0. 5. Unless otherwise noted, address bits Amax-A14 are don't cares.
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6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect address is a read cycle. The system must provide the bank address. 10. (BA) + 0Eh ----> For WS128 = 2244h, WS256 = 2242h, WS512 = 223Dh. (BA) + 0Fh ----> For WS064/128/256/512 = 2200h 11. The data is 0000h for an unlocked sector and 0001h for a locked sector 12. See Table 7.32, Autoselect Addresses on page 32. 13. The Unlock Bypass command sequence is required prior to this command sequence. 14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Program/Erase Suspend command is valid only during a program/ erase operation, and requires the bank address. 16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address. 17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 18. Write Buffer Programming can be initiated after Unlock Bypass Entry. 19. Data is always output at the rising edge of clock. 20. Must be the lowest address. 21. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous settings
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Table 12.2 Sector Protection Commands (Sheet 1 of 2)
Bus Cycles (Note 1 - 6) Cycles First Addr 3 4 1 4 3 2 1 2 3 555 555 SA 555 555 XX 00 XX 555 Data (10) AA AA data AA AA A0 data 90 AA XX 2AA 00/ Program (9) Password 2 XX A0 01/ 02/ 03 Read Password (10) Unlock (9) Protection Command Set Exit Non-Volatile Sector Protection Command Set Entry (5) Program PPB All Erase (8) Status Read Non-Volatile Sector Protection Command Set Exit (7) Global Volatile Sector Protection Freeze Command Set Entry (5) Set PPB Lock Bit Status Read Global Volatile Sector Protection Freeze Command Set Exit (7) Volatile Sector Protection Command Set Entry (5) Set DYB Clear Status Read Volatile Sector Protection Command Set Exit (7) 1 2 XX XX RD(0) 90 XX 00 (BA) 555 4 7 2 00 00 XX PWD 0 25 90 01 00 XX 00 55 PWD 0/ 1/ 2/ 3/ PWD 1 03 00 (BA) 555 02 00 PWD 2 PWD 0 03 01 PWD 3 PWD 1 02 PWD 2 03 PWD 3 00 29 555 60 2AA 2AA 00 55 55 data 555 555 90 40 XX 00 Second Addr 2AA 2AA Data( (10) 55 55 Third Addr 555 555 Data( (10) 88 A0 PA PD Fourth Addr Data( (10) Fifth Addr Data( (10) Sixth Addr Data( (10) Seventh Addr Data( (10)
Command Sequence (Notes) Entry (5) Program Secured Silicon Sector Read Exit (7) Register Command Set Entry (5) Register Bits Program (6) Lock Register Register Bits Read Register Command Set Exit (7) Protection Command Set Entry
3
555
AA
2AA (BA) SA XX
55
C0
2 2 1
XX XX (BA) SA XX
A0 80 RD(0)
00 30
2
90
XX
00
3 2
555 XX
AA A0
2AA XX
55 00
555
50
3 2 2 1 2
555 XX XX (BA) SA XX
AA A0 A0 RD(0) 90
2AA (BA) SA (BA) SA
55 00 01
E0
XX
00
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Table 12.2 Sector Protection Commands (Sheet 2 of 2)
Bus Cycles (Note 1 - 6) Cycles First Addr 2 2 2 1 4 1 555 555 555 RA SA SA Data (10) A0 80 80 RD 25 29 SA WC PA PD WBL PD Second Addr PA SA 555 Data( (10) Data 30 10 Third Addr Data( (10) Fourth Addr Data( (10) Fifth Addr Data( (10) Sixth Addr Data( (10) Seventh Addr Data( (10)
Command Sequence (Notes) Program Sector Erase Chip Erase Accelerated Asynchronous Read Write to Buffer Program Buffer to Flash
Legend X = Don't care RA = Read Address RD = Read Data PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address: WS128P = A22-A14, WS256P = 23-A14 BA = Bank Address: WS128P = A22-A20, and A19; WS256P = A23-A20 CR = Configuration Register data bits D15-D0 PWD3-PWD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password. PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes 1. See Table 7.1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the WS512P only. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. "All PPB Erase" command pre-programs all PPBs before erasure to prevent over-erasure. 9. Entire two bus-cycle sequence must be entered for each portion of the password. 10. Full address range is required for reading password.
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12.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12.3-12.6 within that bank. All reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: CFI Entry command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* Example: CFI Exit command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write CFI entry command */
/* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01). Please contact your sales office for copies of these documents. Table 12.3 CFI Query Identification String
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string QRY Description
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 12.4 System Interface String
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0005h 0009h 000Ah 0000h 0003h 0003h 0003h 0000h VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical Program Time per single word write 2N s (e.g. 30us) Typical Program Time using buffer 2N s (e.g. 300us) (00h = not supported) Typical time for sector erase 2N ms Typical time for full chip erase 2N ms (00h = not supported) Max. Program Time per single word [2N times typical value] Max. Program Time using buffer [2N times typical value] Max. time for sector erase [2N times typical value] Max. time for full chip erase [2N times typical value] (00h = not supported) Description
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Table 12.5 Device Geometry Definition
Addresses 27h 28h 29h 2Ah 2Bh 2Ch Data 0018h (WS128P) 0019h (WS256P) 001Ah (WS512P) 0001h 0000h 0006h 0000h 0003h Device Size = 2N byte Flash Device Interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte] [upper byte] (00h = not supported) Max. number of bytes in multi-byte buffer write = 2N [lower byte] [upper byte] (00h = not supported) Number of Erase Block Regions within device 01h = Uniform Sector; 02h = Boot + Uniform; 03h = Boot + Uniform + Boot Erase Block Region 1 Information (Small Sector Section) 2Dh 2Eh 2Fh 30h 0003h 0000h 0080h 0000h [lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 2 Information (Large Sector Section) 31h 007Dh (WS128P) 00FDh (WS256P) 00FDh (WS512P) 0001h 0000h 0002h [lower byte] - Number of sectors. Description
32h 33h 34h
[upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 3 Information (Small Sector Section)
35h 36h 37h 38h 39h 3Ah 3Bh 3Ch
0003h 0000h 0080h 0000h 0000h 0000h 0000h 0000h
[lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte]
Erase Block Region 4 Information
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Table 12.6 Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Addresses 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0034h Query-unique ASCII string PRI Major CFI version number, ASCII Minor CFI version number, ASCII Address Sensitive Unlock (Bits 1-0) 00b = Required, 01b = Not Required Silicon Technology (Bits 5-2) 0011b = 130nm; 0100b = 110nm; 0101b = 90nm 001010b = 000Ah Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protection per Group 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08h = Advanced Sector Protection; 07h = New Sector Protection Scheme Simultaneous Operation Number of Sectors in all banks except boot bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Write Protect Function 00h = No Boot, 01h = Dual Boot, 02h = Bottom Boot, 03h = Top Boot Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01=Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns (e.g. 10us => n=14) Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns (e.g. 10us => n=14) Erase Suspend Time-out Maximum 2N s Program Suspend Time-out Maximum 2N s Bank Organization: X = Number of banks Description
45h
0101b
46h 47h 48h 49h
0002h 0001h 0000h 0008h 07Bh (WS128P) 0F3h (WS256P) 1E3h (WS512P) 0001h 0002h 0085h
4Ah
4Bh 4Ch 4Dh
4Eh
0095h
4Fh 50h 51h 52h 53h 54h 55h 56h 57h
0001h 0001h 0001h 0008h 0014h 0014h 0005h 0005h 0010h 0007h (WS064P) 000Bh (WS128P) 0013h (WS256P) 0023h (WS512P) 0004h (WS064P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0004h (WS064P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P)
58h
Bank 0 Region Information. X = Number of sectors in bank
59h
Bank 1 Region Information. X = Number of sectors in bank
5Ah
Bank 2 Region Information. X = Number of sectors in bank
5Bh
Bank 3 Region Information. X = Number of sectors in bank
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Table 12.6 Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses 5Ch Data 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 64h 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 000Bh (WS128P) 0013h (WS256P) 0023h (WS512P) Bank 12 Region Information. X = Number of sectors in bank Description Bank 4 Region Information. X = Number of sectors in bank
5Dh
Bank 5 Region Information. X = Number of sectors in bank
5Eh
Bank 6 Region Information. X = Number of sectors in bank
5Fh
Bank 7 Region Information. X = Number of sectors in bank
60h
Bank 8 Region Information. X = Number of sectors in bank
61h
Bank 9 Region Information. X = Number of sectors in bank
62h
Bank 10 Region Information. X = Number of sectors in bank
63h
Bank 11 Region Information. X = Number of sectors in bank
65h
Bank 13 Region Information. X = Number of sectors in bank
66h
Bank 14 Region Information. X = Number of sectors in bank
67h
Bank 15 Region Information. X = Number of sectors in bank
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13. Revision History
Section Revision A6 (November 3, 2006) Features Switching Waveforms Timing Diagrams Revision A7 (November 8, 2006) Features Erase/Program Timing CMOS Compatible Revision A8 (March 9, 2007) Asynchronous Mode Read Changed tCR to tRDY in figures 11.9 through 11.12 Revised Device Geometry table:
* Changed WS512P data to 00FDh * Address 32h - Data changed to 001h * Address 33h - Data changed to 000h * Address 34h - Data changed to 002h
Description
Removed Zero Hold mode Revised VCC Power-up diagram Changed tCR to tRDY in figure 11.7 and figure 11.8 Updated Effective Write Buffer Programming Per Word tESL changed to Max tPSL changed to Max Removed Note 2 from table.
Common Flash Memory Interface
Revised CFI table: removed Uniform Bottom, Uniform Top, and All sectors for Address 4Fh DC Characteristics Revision A9 (March 28, 2007) DC Characteristics Synchronous/Burst Read Asynchronous Mode Read Revision A10 (April 20, 2007) Removed wait state below 14 MHz, wait state 2 AC Characteristics Added additional wait state to all wait state frequency in table 11.4 Added Continuous Burst Mode Synchronous Wait State Requirement table Revised Burst Access Time to (WS-1) * tCK + (tBACC) Revision A11 (September 28, 2007) Data Sheet Status Global Latency Configuration Registers AC Characteristics DC Characteristics Changed to Production Changed all 108 MHz to 104 MHz Added 10 wait state and 11 wait state latency tables Added two more configurations to CR0.11 for 10th and 11th rising CLK edge Revised tCES to 6 ns Revised tAVD to tCLK Changed description of ICC2 to VCC Active Program/Erase Current Change descritpion of ICC5 to VCC Active Current (Read while Program/Erase) Revised: tERS to 40 ns Erase/Program Timing and Performance tESL to 40 ns tPSL to 40 ns tPRS to 40 ns Output Slew Rate Deleted Programmable Outuput Slew Rate Control section Revised ICCB for 108 MHz frequencies to TBA Revised tRACC to 7.6 ns Revised tAAVDH to 4 ns Revised ICCB Burst table
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Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006-2007 Spansion Inc. All rights reserved. Spansion(R), the Spansion Logo, MirrorBit(R), MirrorBit(R) EclipseTM, ORNANDTM, HD-SIMTM and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
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